1. Technical Field
The present invention relates to a switching power supply device and, in particular, to a technique for adjusting a dead time of a gate drive circuit used in the switching power supply device.
2. Description of the Related Art
Resonant switching power supply devices which make use of voltage-current resonance phenomena to perform zero voltage switching (ZVS), thereby to reduce losses on switching and to improve the efficiency have been used. FIG. 10 shows one example of a circuit configuration of a resonant switching power supply device. Operations of the resonant switching power supply device shown in FIG. 10 are disclosed, for example, in JP-A-8-289640 and JP-A-2007-6614. A switching power supply device includes a series circuit in which high side and low side switching elements are connected between a positive electrode and a negative electrode of a direct-current power supply, and these switching elements are switched alternately to obtain an output from an intermediate connection point thereof. In a power supply device such as the switching power supply, as described in JP-A-8-289640 and JP-A-2007-6614, a dead time is set for a gate signal so that the high side and the low side switching elements will not cause a short-circuit on switching. In most cases, the dead time is set by a control circuit for generating a gate signal (hereinafter, referred to as a gate signal control circuit).
Hereinafter, a more detailed description will be given for the switching operation of the switching power supply device 1 shown in FIG. 10 with reference to FIG. 11 to FIG. 13. The direction of each arrow shown in FIG. 10 indicates a positive direction of an operating waveform.
As shown in FIG. 10, the switching power supply device 1 includes a first series circuit including a switching element Q1 (a high side switching element) and a switching element Q2 (a low side switching element) which are connected to the both ends of a direct current power supply Vin. Each of the switching element Q1 and the switching element Q2 includes, for example, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The switching power supply device 1 further includes a second series circuit including a leakage inductance Lri, a primary winding N11 of an output transformer T1 (primary winding inductance Lp) and a current resonance capacitor Cri is connected in parallel to the switching element Q2. The direct current power supply Vin includes, for example, a power supply circuit configured to obtain a direct current voltage, in which a commercial alternating current power supply is subjected to full-wave rectification and to smoothing by a smoothing capacitor.
A series circuit including a diode Do and a smoothing capacitor Co is connected in parallel to a secondary winding N12 of the output transformer T1, and the primary winding N11 and the secondary winding N12 of the output transformer T1 are wound around so as to give voltage polarity as indicated by an illustrated polarity mark, thus constituting a rectifying smoothing circuit. An output voltage of the rectifying smoothing circuit obtained through rectification and smoothing by the diode Do and the smoothing capacitor Co is given as an output voltage of the switching power supply device 1, thereby supplying a direct current power to load RL connected in parallel to the smoothing capacitor Co. A voltage feedback circuit 2 detects an output voltage of the rectifying smoothing circuit and outputs it to gate power supplies VpH, VpL. Based on a detected voltage from the voltage feedback circuit 2, the gate power supplies VpH, VpL generate gate signals, thereby controlling the output voltage of the switching power supply device 1. The gate power supplies VpH, VpL are provided with a gate signal control circuit for generating gate signals, and dead time for preventing short-circuits on switching is set in the gate signal control circuit.
FIG. 10 shows an example where an N channel MOSFET is used as the switching elements Q1 and Q2. The gate power supplies VpH, VpL are connected to the gates of the switching elements Q1 and Q2 via gate resistors Rg1 and Rg2, by which the switching elements Q1 and Q2 are controlled for ON/OFF operation. Further, parasitic capacitors Cgd1 (gate-drain capacitor of Q1), Cgs1 (gate-source capacitor of Q1), Cds1 (drain-source capacitor of Q1), Cgd2 (gate-drain capacitor of Q2), Cgd2 (gate-source capacitor of Q2) and Cds2 (drain-source capacitor of Q2), a body diode DH of Q1 (acting as a high side feedback diode) and a body diode DL of Q2 (acting as a low side feedback diode) are connected between the gates, sources and drains of the switching elements Q1 and Q2.
<ON-Time Operation of Switching Element Q2>
A portion (a) of FIG. 11 shows operations when the low side switching element Q2 is shifted from OFF to ON. Further, FIG. 12 shows an enlarged view of the portion (a) of FIG. 11.
The portion (a) shown in FIG. 11 shows operating waveforms when the high side switching element Q1 is shifted from ON to OFF and the low side switching element Q2 is shifted from OFF to ON.
Operating waveforms shown in FIG. 11 include sequentially from the top a drain-source voltage waveform Vds1 of the switching element Q1, a gate signal Vg1 of the switching element Q1, a drain-source voltage waveform Vds2 of the switching element Q2, a gate signal Vg2 of the switching element Q2, a voltage VCgs2 of gate-source capacitor Cgs2 of the switching element Q2, a current ICds2 of drain-source capacitor Cds2 of the switching element Q2, a current ICgd2 of gate-drain capacitor Cgd2 of the switching element Q2, a resonance current ICri of the current resonance capacitor Cri, and a current IDL of the body diode DL.
The operating waveforms shown in FIG. 12 are enlargements corresponding to the portion (a) shown in FIG. 11, and they are sequentially from the top a drain-source voltage waveform Vds2 of the switching element Q2, a gate signal Vg2 of the switching element Q2, a voltage VCgs2 of gate-source capacitor Cgs2 of the switching element Q2, a current ICds2 of drain-source capacitor Cds2 of the switching element Q2, a current ICgd2 of gate-drain capacitor Cgd2 of the switching element Q2, a resonance current ICri of the current resonance capacitor Cri, and a current IDL of the body diode DL.
Time points t1 to t6 shown in FIG. 11 and FIG. 12 denote the time points as follows:
t1: point at which the gate signal Vg1 falls down;
t2: point at which the current IDL of body diode DL starts to conduct;
t3: point at which the gate signal Vg2 rises up;
t4: point at which the gate signal Vg2 falls down;
t5: point at which the current IDH (not illustrated) of body diode DH starts to conduct; and
t6: point at which the gate signal Vg1 rises up.
At the time point t1 at which the gate signal Vg1 falls down and when the high side switching element Q1 is shifted from an ON state to an OFF state, the drain-source voltage Vds1 of the high side switching element Q1 conducts a quasi-voltage resonance operation. In this instance, parasitic capacitors (Cds1, Cds2, Cgd1, Cgd2) of the switching elements Q1 and Q2 are charged and discharged by a resonance current ICri (high side Cds1 and Cgd1 are charged, while low side Cds2 and Cgd2 are discharged). At this time, the ICri is divided into a high side and a low side (where the switching elements Q1 and Q2 are equal in parasitic capacitor, the ICri is equally divided into two). The divided resonance current is further divided into Cds1 and Cgd1 on the high side and into Cds2 and Cgd2 on the low side. This proportion equals a capacitance ratio of the capacitors Cds1 to Cgd1 on the high side and a capacitance ratio of the capacitors Cds2 to Cgd2 on the low side. In this instance, a resonance current flown into the Cgd2 charges the gate-source capacitor Cgs2 of the switching element Q2 in a negative direction. This charge voltage is decided by a product Rg2×ICgd2 of the current ICgd2 flowing into the gate resistor Rg2 and the capacitor Cgd2 of the switching element Q2.
At the time point 2 at which the parasitic capacitor of the low side switching element Q2 is completely discharged, a body diode DL connected in inverse-parallel to the low side switching element Q2 is conducted. Conduction of the body diode DL allows a resonance current to flow via the body diode DL, thereby no resonance current flows through the parasitic capacitor Cds2 or Cgd2.
In this instance, at the time point t3 in a period Tc during which the body diode DL is conducted, the low side switching element Q2 is allowed to switch on, thereby performing zero voltage switching (ZVS). However, a period from t1 to t3, that is, from the time when a gate signal Vg1 of the high side switching element Q1 falls down at the time point t1 to the time when a gate signal Vg2 of the switching element Q2 rises up at the time point t3 is secured as a dead time td1 on a gate signal control circuit, thereby eliminating a possibility that the high side switching element Q1 and the low side switching element Q2 are conducted simultaneously and damaged.
<OFF Time Operation of Switching Element Q2>
A portion (b) of FIG. 11 shows operations when the low side switching element Q2 is shifted from ON to OFF. FIG. 13 shows an enlarged view of the portion (b) of FIG. 11(b).
The portion (b) of FIG. 11 shows operating waveforms when the high side switching element Q1 is shifted from OFF to ON and the low side switching element Q2 is shifted from ON to OFF.
The operating waveforms shown in FIG. 13 are enlargements of the portion (b) of FIG. 11, and similar to FIG. 12, FIG. 13 shows sequentially from the top a drain-source voltage waveform Vds2 of the switching element Q2, a gate signal Vg2 of the switching element Q2, a voltage VCgs2 of gate-source capacitor Cgs2 of the switching element Q2, a current ICds2 of drain-source capacitor Cds2 of the switching element Q2, a current ICgd2 of gate-drain capacitor Cgd2 of the switching element Q2, a resonance current ICri of the current resonance capacitor Cri, and a current IDL of the body diode DL.
Time points t4 to t6 shown in FIG. 13 denote, as shown in FIG. 11 and FIG. 12, the time points as follows:
t4: point at which the gate signal Vg2 falls down;
t5: point at which the current IDH (not illustrated) of body diode DH starts to conduct; and
t6: point at which the gate signal Vg1 rises up.
The gate signal Vg2 falls down at the time point t4, and when the low side switching element Q2 is shifted from an ON state to an OFF state, the drain-source voltage Vds2 of the low side switching element Q2 conducts a quasi-voltage resonance operation. At this time, parasitic capacitors (Cds1, Cds2, Cgd1, Cgd2) of the switching elements Q1 and Q2 are charged and discharged by a resonance current ICri (high side Cds1 and Cgd1 are discharged, while low side Cds2 and Cgd2 are charged). At this time, the ICri is divided into a high side and a low side (where the switching elements Q1 and Q2 are equal in parasitic capacitor, the ICri is equally divided into two). The divided resonance current is further divided into Cds1 and Cgd1 on the high side and into Cds2 and Cgd2 on the low side. This proportion equals a capacitance ratio of the capacitors Cds1 to Cgd1 on the high side and a capacitance ratio of the capacitors Cds2 to Cgd2 on the low side. At this time, a resonance current flown into the Cgd2 charges the gate-source capacitor Cgs2 of the switching element Q2 in a positive direction. This charge voltage is decided by a product Rg2×ICgd2 of the current ICgd2 flowing into the gate resistor Rg2 and the capacitor Cgd2 of the switching element Q2.
At the time point t5, when charge of the parasitic capacitor of the low side switching element Q2 is completed, at the same time, the parasitic capacitor of the high side switching element Q1 is also completely discharged. A body diode DH connected in inverse-parallel to the high side switching element Q1 is conducted. Conduction of the body diode DH allows a resonance current to flow via the body diode DH, thereby no resonance current flows through the drain-source capacitors Cds1 and Cgd1.
In this instance, in a period Td (an operating waveform of IDH is not illustrated) during which the body diode DL is conducted, the high side switching element Q1 is allowed to turn on, thereby performing zero voltage switching (ZVS). However, a period from t4 to t6, that is, from the time when a gate signal Vg2 of the low side switching element Q2 falls down at the time point 4 to the time when a gate signal Vg1 of the switching element Q1 rises up at the time point 6 is secured as a dead time td2 on a gate signal control circuit, thereby eliminating a possibility that the high side switching element Q1 and the low side switching element Q2 are conducted simultaneously and damaged.
As described above, in the switching power supply device 1, a gate signal control circuit is used to set a dead time td, thereby supplying a gate signal Vg to the gates of the switching elements Q1 and Q2. Further, in order to turn the switching elements Q1 and Q2 on quickly after the dead time, a small value of the gate resistor is usually selected, as disclosed for example, in JP-A-2003-189592.